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| ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 1 ? copyright 2006?2015 xilinx, the xilinx logo, artix, ise, kint ex, spartan, virtex, vivado, zynq, and other designated brands i ncluded herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. ?product obsolete / under obsolescence? features ? in-system programmable prom for configuration of xilinx fpgas ? low-power advanced cm os nor flash process ? endurance of 20,000 program/erase cycles ? operation over full milit ary temperature range (?55c to +125c) ? ieee standard 1149. 1/1532 boundar y-scan (jtag) support for programming, prototyping, and testing ? jtag command initiation of standard fpga configuration ? cascadable for storing longer or multiple bitstreams ? dedicated boundary-scan (jtag) i/o power supply (v ccj ) ? i/o pins compatible with voltage levels ranging from 1.8v to 3.3v ? design support using the xilinx alliance ise? and foundation ise series software packages ? xqf32p ? 1.8v supply voltage ? serial or parallel fpga configuration interface (upto33mhz) ? available in small-footprint vog48 package ? design revision technology enables storing and accessing multiple design revisions for configuration ? built-in data decompress or compatible with xilinx advanced compression technology description this data sheet describes the defense-grade version of the platform flash series of in-system programmable configuration proms. available in 32 megabit (mbit) density, this prom provides an easy-to-use, cost-effective, and reprogrammable method for storing large xilinx fpga conf iguration bitstreams . the 32-mbit prom supports master serial, slave serial, master selectmap, and slave selectmap fpga configuration modes ( figure 1 ). defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 product specification ta bl e 1 : xilinx defense grade platform flash prom features device density v ccint v cco range v ccj range packages program in-system via jtag serial config. parallel config. design revisioning compression xqf32p 32 mbit 1.8v 1.8v ? 3.3v 2.5v ? 3.3v vog48 ??? ? ? x-ref target - figure 1 figure 1: xqf32p platform flash prom block diagram clkout ceo data (d0) ( s eri a l/p a r a llel mode) d[1:7] (p a r a llel mode) tck tm s tdi tdo clk ce en_ext_ s el oe/re s et bu s y d a t a d a t a addre ss rev_ s el [1:0] cf control a nd jtag interf a ce memory o s c s eri a l or p a r a llel interf a ce decompre ss or d s 541_01_111706 s e n d f e e d b a c k
defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 2 ?product obsolete / under obsolescence? when the fpga is in master serial mode, it generates a configuration clock that drives the prom. with cf high, a short access time after ce and oe are enabled, data is available on the prom data (d0) pin that is connected to the fpga din pin. new data is available a short access time after each rising clock edge. the fpga generates the appropriate number of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are both clocked by an external clock source, or optionally, the prom can be used to drive the fpga?s configuration clock. the xqf32p defense-grade version of the platform flash pr om also supports master selectmap and slave selectmap (or slave parallel) fpga configuration modes. when the fpga is in master selectmap mode, the fpga generates a configuration clock that drives the pr om. when the fpga is in slave selectma p mode, either an external oscillator generates the configuration clock that drives the prom and the fpga, or optionally, the xqf32p prom can be used to drive the fpga?s configuration clock. with busy low and cf high, after ce and oe are enabled, data is available on the prom data (d0-d7) pins. new data is available a short access time after each rising clock edge. the data is clocked into the fpga on the following rising edge of the cclk. a free-running oscillator c an be used in the slave parallel /slave selecmap mode. the xqf32p defense-grade version of the platform flash pr om provides additional advanced features. a built-in data decompressor supports utilizing co mpressed prom files, and design revisioning allows multiple design revisions to be stored on a single prom or stored across several proms. for design revisioning, external pins or internal control bits are used to select the active design revision. multiple platform flash prom devices can be cascaded to support the larger configuration files required when targeting larger fpga devices or targeting mult iple fpgas daisy chained toge ther. when utilizing the advanced features for the xqf32p platform flash prom, such as design revisioning, programming files which span cascaded prom devices can only be created for cascaded chains containing only xqf32p proms. the platform flash proms are co mpatible with all of the existing fpga device families. the xqf32p platform flash prom capacity is 33,554,432 configuration bits. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 3 ?product obsolete / under obsolescence? programming in-system programming in-system programmable proms can be programmed individua lly, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin jtag protocol as shown in figure 2 . in-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. the programming data sequence is delivered to the device usin g either xilinx impact software and a xilin x download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format, including automatic test equipment. during in-system programming, the ceo output is driven high. all other outputs are held in a high-imp edance state or held at clamp levels during in-system programming. in-system programming is fully supported across the recommended operating voltage and temperature ranges. external programming in traditional manufacturing environments, third-party device programmers can program platform flash proms with an initial memory image before the proms are assembled onto boards. contact a preferred third-party programmer vendor for platform flash prom support information. a sample list of third-party programmer vendors with platform flash prom support is available on the xilinx web page for third-party programmer device support . see ug161 , platform flash prom user guide , for the prom data file format required for programmers. pre-programmed proms can be assembled onto boards using the typical soldering process guidelines in ug112 , device package user guide . a pre-programmed prom?s memory image can be updated after board assembly using an in-system programming solution. reliability and endurance xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in -system program/erase cycles and a minimum data retention of 20 years. each device meet s all functional, performance, and data retention specifications within this endurance limit. design security the xilinx in-system programmable platform flash prom device s incorporate advanced data security features to fully protect the fpga programming data against unauthorized reading via jtag. the xqf32p proms can also be programmed to prevent inadvertent writing via jtag. ta bl e 2 shows the security settings available for the xqf32p prom. x-ref target - figure 2 figure 2: jtag in-system programming operation (a) solder device to pcb (b) program using download cable d s 541_02_111706 gnd v cc (a) (b) s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 4 ?product obsolete / under obsolescence? read protection the read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied via jtag. read protection does not prevent write operations. for the xqf32p prom the read protect security bit can be set for individual design revisions, and resetting the read pr otect bit requires erasing the particular design revision. write protection the xqf32p prom device also allows the user to write protect (or lock) a particular design revision to prevent inadvertent erase or program operations. once set, the write protect security bit for an individual design revision must be reset (using th e unlock command followed by isc_erase command) before an erase or prog ram operation ca n be performed. ieee 1149.1 boundary-scan (jtag) the platform flash prom family is compatible with the i eee 1149.1 boundary-sc an standard and the ieee 1532 in-system configuration standard. a test access port (tap) and registers are provided to support all required boundary scan instructions, as well as many of the opti onal instructions specified by ieee std. 1149.1. in additi on, the jtag interface is used to implement in-system programming (isp) to facilitate configuration, erasur e, and verification operations on the platform flash prom device. ta bl e 3 lists the required and optional boundary-scan instructions supported in the platform flash proms. refer to the ieee std. 1149. 1 specification for a comple te description of boundary- scan architecture and the required and optional instructions. note: the xqf32p jtag tap pause states are not fully compliant with the jtag 1149.1 specification. if a temporary pause of a jtag shift operation is required, then st op the jtag tck clock and maintain the jtag tap within the jtag shift-ir or shift-dr tap st ate. do not transition the xqf32p jtag tap through the jtag pause-ir or pause-dr tap state to temporarily pause a jtag shift operation. ta bl e 2 : xqf32p design revision data security options read protect write protect read/verify inhibited program inhibited erase inhibited reset (default) reset (default) ? ? ? reset (default) set ? ?? set reset (default) ? ?? set set ??? ta bl e 3 : platform flash prom boundary scan instructions boundary-scan command xqf32p ir[15:0] (hex) instruction description required instructions bypass ffff enables bypass. sample/preload 0001 enables boundary-scan sam ple/preload operation. extest 0000 enables boundary-scan extest operation. optional instructions clamp 00fa enables boundary-scan clamp operation. highz 00fc places all outputs in high-impedance state simultaneously. idcode 00fe enables shifting out 32-bit idcode. usercode 00fd enables shifting out 32-bit usercode. platform flash prom specific instructions config 00ee initiates fpga configuration by pulsing cf pin low once (for the xqf32p, this command also resets the selected design revision based on either the external rev_sel[1:0] pins or on the internal design revision selection bits). (1) notes: 1. for more information see initiating fpga configuration, page 9 . s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 5 ?product obsolete / under obsolescence? instruction register the instruction register (ir) for the platform flash prom is connected between tdi and tdo during an instruction scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruction registe r from tdi. xqf32p instruction register (16 bits wide) the instruction register (ir) for the xqf32p prom is sixte en bits wide and is connected between tdi and tdo during an instruction scan sequence. the detaile d composition of the instruction capture pattern is illustrated in ta bl e 4 . the instruction capture pattern shifted out of the xqf32p device includes ir[15:0]. ir[15:9] are reserved bits and are set to a logic 0. the isc error field, ir[8:7], contains a 10 when an isc operation is a success; otherwise a 01 when an in-system configuration (isc) operation fails. the erase/program (er/prog) error field, ir[6:5], contains a 10 when an erase or program operation is a success; otherwise a 01 when an erase or program operation fails. the erase/program (er/prog) status field, ir[4], contains a logic 0 when the device is bu sy performing an erase or programming operation; otherwise, it contains a logic 1. the isc status field, ir[3], contains logi c 1 if the device is currently in in-system configuration (isc) mode; otherwise, it contains logic 0. the done field, ir [2], contains logic 1 if the sampled design revision has been successfully programmed; otherwise, a logic 0 indicates incomplete programming. the remaining bits ir[1:0] are set to 01 as defined by ieee std. 1149.1. boundary scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sample/preload, and clamp instructions. each output pin on the platform flash prom has two register stages which contribute to the boundary-scan register, while each input pin has only one register stage. the bidirectional pins have a total of three register stages which contribute to the boundary-scan register. for each output pin, the register stage nearest to tdi controls and observes th e output state, and the second stage closest to tdo controls and observes the high-z enable state of the output pin. for each inp ut pin, a single register stage controls and observes the input st ate of the pin. the bidirectional pin combines the three bits, t he input stage bit is first, followed by the output stage bit and finally the output enable stage bit. the output enable stage bit is cl osest to tdo. see the xqf32p pin names and descriptions tables in pinouts and pin descriptions, page 23 for the boundary-scan bit order for all connected device pins, or see the appropriate bsdl file for the complete boundary-scan bit order description under the attribute boundary_register section in the bsdl file. the bit assigned to boundary-scan cell 0 is the lsb in the boundary-scan register, and is the register bit closest to tdo. identification registers idcode register the idcode is a fixed, vendor-assigned value that is used to el ectrically identify the manufacturer and type of the device bein g addressed. the idcode register is 32 bits wide. the idcode register can be shifted out for examination by using the idcode instruction. the idcode is available to any other system component via jtag. the idcode register has th e following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where: v = the die version number f = the prom family code a = the specific platform flash prom product id c = the xilinx manufacturer's id the lsb of the idcode register is alwa ys read as logic 1 as defined by ieee std. 1149.1. the idcode register value for the xq32pplatform flash prom is defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 6 ?product obsolete / under obsolescence? usercode register the usercode instruction gives access to a 32-bit user prog rammable scratch pad typically used to supply information about the device's programmed contents. by using the usercode instruction, a user-programmable identification code can be shifted out for examination. this code is loaded into the usercode register during programming of the platform flash prom. if the device is blank or was not loaded during programming, the usercode register contains ffffffffh . customer code register for the xqf32p platform flash prom, in addition to the u sercode, a unique 32-byte customer code can be assigned to each design revision enabled for the prom. the customer code is set during programming, and is typically used to supply information about the design revision contents. a private jtag instruction is required to read the customer code. if the prom is blank, or the customer code for the selected design revision was not loaded during programming, or if the particular design revision is erased, the customer code contains all ones. platform flash prom tap characteristics the platform flash prom family perform s both in-system programmi ng and ieee 1149.1 boundary-scan (jtag) testing via a single 4-wire test access port (tap). this simplifies system designs and allows standard au tomatic test equipment (ate) to perform both functions. the ac characteristics of the platform flash prom tap are described as follows. tap timing figure 3 shows the timing relationships of the tap signals. th ese tap timing characteristics are identical for both boundary-scan and isp operations. tap ac parameters ta bl e 5 shows the timing parameters for the tap waveforms shown in figure 3 . x-ref target - figure 3 figure 3: test access port timing ta bl e 5 : test access port timing parameters symbol description min max units t ckmin tck minimum clock period when v ccj = 2.5v or 3.3v 100 ? ns t mss tms setup time when v ccj = 2.5v or 3.3v 10 ? ns t msh tms hold time when v ccj = 2.5v or 3.3v 25 ? ns t dis tdi setup time when v ccj = 2.5v or 3.3v 10 ? ns t dih tdi hold time when v ccj = 2.5v or 3.3v 25 ? ns t dov tdo valid delay when v ccj = 2.5v or 3.3v ? 30 ns tck t ckmin t m ss tm s tdi tdo t m s h t dih t dov t di s d s 541_0 3 _111706 s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 7 ?product obsolete / under obsolescence? additional features for the xqf32p internal oscillator the 32-mbit xqf32p platform flash proms include an optional internal oscillator which can be used to drive the clkout and data pins on fpga configuration interface. the inter nal oscillator can be enabled wh en programming the prom, and the oscillator can be set to either the default frequency or to a slower frequency ( xqf32p prom as configuration master with internal oscillator as clock source, page 19 ). clkout the 32-mbit xqf32p platform flash proms include the programmable option to enable the clkout signal which allows the prom to provide a source synchronous clock aligned to the data on the configuration interface. the clkout signal is derived from one of two clock sources: the clk input pin or the in ternal oscillator. th e input clock source is selected during the prom programming sequence. output data is available on the rising edge of clkout. the clkout signal is enabled during programming, and is active when ce is low and oe/reset is high. on ce rising edge transition, if oe/reset is high and the prom terminal count has not been reached, then clkout remains active for an additional eights clock cycles be fore being disabled. on a oe/reset falling edge transition, clkout is immediately disabled. when disabled, the clkout pin is put into a high-impedance state and should be pulled high externally to provide a known state. when cascading platform flash proms with clkout enabled, after completing it's data transfer, the first prom disables clkout and drives the ceo pin enabling the next prom in the prom chain. the next prom begins driving the clkout signal once that prom is enabled and data is available for transfer. during high-speed parallel configuration without compression, the fpga drives the busy signal on the configuration interface. when busy is asserted high, the proms internal address counter stops incrementing, and the current data value is held on the data outputs. wh ile busy is high, the prom continues dr iving the clkout signal to the fpga, clocking the fpga?s configuration logic. when the fpga deassert s busy, indicating that it is ready to receive additional configuration data, the prom begins driving new data onto the configuration interface. decompression the 32-mbit xqf32p platform flash proms include a built-in data decompressor compatible with xilinx advanced compression technology. compressed platform flash prom file s are created from the target fpga bitstream(s) using the impact software. only slave serial and slave selectmap (parallel) configuration modes are supported for fpga configuration when using a xqf32p prom programmed with a compressed bitstream. compression rates vary depending on several factors, including the target device family and the target design contents. the decompression option is enabled during the prom programmi ng sequence. the prom decompresses the stored data before driving both clock and data onto the fpga's configuration interface. if decompression is enabled, then the platform flash clock output pin (clkout) must be us ed as the clock signal for the configurat ion interface, drivin g the target fpga's configuration clock input pin (cclk). either the prom's clk input pin or the intern al oscillator must be selected as the source for clkout. any target fpga connected to the prom must operate as slave in the configuration chain, with the configuration mode set to slave serial mode or slave selectmap (parallel) mode. when decompression is enabled, the clkout signal bec omes a controlled clock output with a reduced maximum frequency. when decompressed data is not ready, the clkout pin is put into a high-z state and must be pulled high externally to provide a known state. the busy input is automatically disa bled when decompression is enabled. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 8 ?product obsolete / under obsolescence? design revisioning design revisioning allows the user to create up to four uni que design revisions on a single prom or stored across multiple cascaded proms. design revisioning is supported for the xqf32p platform flash prom in both serial and parallel modes. design revisioning can be used with compressed prom files, and also when the clkout feature is enabled. the prom programming files along with the revision information files ( .cfi ) are created using the impact software. the .cfi file is required to enable design revision programming in impact. a single design revision is composed of from 1 to n 8-mbit memory blocks. if a single design revision contains less than 8 mbits of data, then the remaining space is padded with all ones. a larger design revision can span several 8-mbit memory blocks, and any space remaining in the last 8-mbit memory block is padded with all ones. ? a single 32-mbit prom contains four 8-mbit memory blocks, and can therefore store up to four separate design revisions: one 32-mbit design revision, two 16-mbit design revi sions, three 8-mbit design revisions, four 8-mbit design revisions, and so on. ? because of the 8-mbit minimum size requirement for each revision, a single 16-mbit prom can only store up to two separate design revisions: one 16-mbit design revision, one 8-mbit design revision, or two 8-mbit design revisions. ? a single 8-mbit prom can store only one 8-mbit design revision. larger design revisions can be split over several cascaded proms. for example, two 32-mbit proms can store up to four separate design revisions: one 64-mbit design revision, two 32 -mbit design revisions, three 16-mbit design revisions, four 16-mbit design revisions, and so on. see figure 4 for a few basic examples of how multiple revisions can be stored. the design revision partitioning is handled automatically during file generation in impact. during the prom file creation, each design revision is assigned a revision number: revision 0 = 00 revision 1 = 01 revision 2 = 10 revision 3 = 11 after programming the platform flash prom with a set of desi gn revisions, a particular design revision can be selected using the external rev_sel[1:0] pins or using the internal programmable design revision control bits. the en_ext_sel pin determines if the external pins or internal bits are used to select the design revision. when en_ext_sel is low, design revision selection is controlled by the external revision select pins, rev_sel[1:0]. when en_ext_sel is high, design revision selection is controlled by the internal programmable revision select control bits. during power up, the design revision selection inputs (pins or control bits) are sampled inte rnally. after power up, the design revision selection inputs a re sampled again when any of the following events occur: ? on the rising edge of ce ? on the falling edge of oe/reset (when ce is low) ? on the rising edge of cf (when ce is low) ? when reconfiguration is initiated by using the jtag config instruction. the data from the selected design revision is th en presented on the fpga configuration interface. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 9 ?product obsolete / under obsolescence? initiating fpga configuration the options for initiating fpga configuration via the platform flash prom include: ? automatic configuration on power up ? applying an external prog_b (or program ) pulse ? applying the jtag config instruction following the fpga?s power-on sequence or the assertion of the prog_b (or program ) pin the fpga?s configuration memory is cleared, the configuration mode is selected, and th e fpga is ready to accept a new configuration bitstream. the fpga?s prog_b pin can be controlled by an external source, or alternatively, the platform flash proms incorporate a cf pin that can be tied to the fpga?s prog_b pin. executing the config instruction through jtag pulses the cf output low once for 300-500 ns, resetting the fpga and initiating configuration. the impact software can issue the jtag config command to initiate fpga configuration by setting the load fpga option. when using the xqf32p platform flash prom with design revisioning enabled, the cf pin should always be connected to the prog_b (or program ) pin on the fpga to ensure that the current design revision selection is sampled when the fpga is reset. the xqf32p prom samples the current design revision selection from the external rev_sel pins or the internal programmable revision select bits on the rising edge of cf . when the jtag config command is executed, the xqf32p samples the new design revision selection before initiating the fpga configuration sequence. when using the xqf32p platform flash prom without design revisioning, if the cf pin is not connected to the fpga prog_b (or program ) pin, then the xqf32p cf pin must be tied high. x-ref target - figure 4 figure 4: design revision storage examples rev 0 ( 8 m b it s ) rev 1 ( 8 m b it s ) rev 2 ( 8 m b it s ) rev 3 ( 8 m b it s ) rev 0 ( 8 m b it s ) rev 1 ( 8 m b it s ) rev 2 (16 m b it s ) rev 0 (16 m b it s ) rev 1 (16 m b it s ) rev 0 ( 8 m b it s ) rev 1 (24 m b it s ) rev 0 ( 3 2 m b it s ) 4 de s ign revi s ion s3 de s ign revi s ion s 2 de s ign revi s ion s 1 de s ign revi s ion ( a ) de s ign revi s ion s tor a ge ex a mple s for a s ingle xqf 3 2p prom rev 0 (16 m b it s ) rev 1 (16 m b it s ) rev 2 (16 m b it s ) rev 3 (16 m b it s ) rev 0 (16 m b it s ) rev 1 (16 m b it s ) rev 2 ( 3 2 m b it s ) rev 0 ( 3 2 m b it s ) rev 1 ( 3 2 m b it s ) rev 0 (16 m b it s ) rev 1 (16 m b it s ) rev 0 ( 3 2 m b it s ) 4 de s ign revi s ion s3 de s ign revi s ion s 2 de s ign revi s ion s 1 de s ign revi s ion ( b ) de s ign revi s ion s tor a ge ex a mple s s p a nning two xqf 3 2p prom s prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 rev 0 ( 3 2 m b it s ) rev 1 ( 3 2 m b it s ) prom 1 prom 1 prom 1 prom 1 prom 1 d s 541_04_070906 s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 10 ?product obsolete / under obsolescence? reset and power-on reset activation at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified v ccint rise time. if the power supply cannot meet this requirement, then the device might not perform power-on reset properly. during the power-up sequence, oe/reset is held low by the prom. on ce the required supplies have reached their respective por (power on reset) thresholds, the oe/reset release is delayed (t oer minimum) to allow more margin for the power supp lies to stabilize before initiating configuration. the oe/reset pin is connected to an external 4.7 k pull-up resistor and also to the target fpga's init pin. for syste ms utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the oe/reset pin low. when oe/reset is released, the fpga?s init pin is pulled high allowing the fpga's configuration sequence to begin. if the power drops below the power-down threshold (v ccpd ), the prom resets and oe/reset is again held low until the after the por threshold is reached. oe/reset polarity is not programmable. these power-up requirements are shown graphically in figure 5 . for a fully powered platform flash pr om, a reset occurs whenever oe/reset is asserted (low) or ce is deasserted (high). the address counter is reset, ceo is driven high, and the remaining outputs are placed in a high-impedance state. note: the xqf32p prom requires both v ccint to rise above its por threshold and for v cco to reach the recommended operating voltage level before releasing oe/reset . i/o input voltage tolerance and power sequencing the i/os on each re-programmable platform flash prom are fu lly 3.3v tolerant. this allows 3v cmos signals to connect directly to the inputs without damage. the core power supply (v ccint ), jtag pin power supply (v ccj ), output power supply (v cco ), and external 3v cmos i/o signals can be applied in any order. standby mode the prom enters a low-power standby mode whenever ce is deasserted (high). in standby mode, the address counter is reset, ceo is driven high, and the remaining outputs are placed in a high-impedance state regardless of the state of the oe/reset input. for the device to remain in the low-power standby mode, the jtag pins tms, tdi, and tdo must not be pulled low, and tck must be stopped (high or low). when using the fpga done signal to drive the prom ce pin high to reduce standby power after configuration, an external pull-up resistor should be used. typically a 330 pull-up resistor is used, but refer to the appropriate fpga data sheet for the recommended done pin pull-up value. if the done circuit is connected to an led to indicate fpga configuration is complete, and is also connected to the prom ce pin to enable low-power standby mode, then an external buffer should be used to drive the led circuit to ensure valid transitions on the prom?s ce pin. if low-power standby mode is not required for the prom, then the ce pin should be connected to ground. x-ref target - figure 5 figure 5: platform flash prom power-up requirements t oer v ccint v ccpor v ccpd 200 s r a mp 50 m s r a mp t oer t r s t time (m s ) a s low-r a mping v ccint su pply m a y s till b e b elow the minim u m oper a ting volt a ge when oe/re s et i s rele as ed. in thi s c as e, the config u r a tion s e qu ence m us t b e del a yed u ntil b oth v ccint a nd v cco h a ve re a ched their recommended oper a ting condition s . recommended operatin g ran g e delay or re s tart confi g uration d s 541_05_012011 s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 11 ?product obsolete / under obsolescence? ta bl e 6 shows the truth table of the xqf32p prom inputs and outputs. ta bl e 6 : truth table for xqf32p prom control inputs control inputs internal address outputs oe/reset ce cf busy (5) data ceo clkout icc high low high low if address < tc (2) and address < ea (3) : increment active high active active if address < tc (2) and address = ea (3) : don't change high-z high high-z reduced else if address = tc (2) : don't change high-z low high-z reduced high low high high unchanged active and unchanged high active active high low x (1) reset (4) active high active active low low x (1) x (1) held reset (4) high-z high high-z active x (1) high x (1) x (1) held reset (4) high-z high high-z standby notes: 1. x = don?t care. 2. tc = terminal count = highest address value. 3. for the xqf32p with design revisioning enabled, ea = end address (last address in the selected design revision). 4. for the xqf32p with design revisioning enabled, reset = address reset to the beginning address of the selected bank. if desig n revisioning is not enabled, then reset = address reset to address 0. 5. the busy input is only enabled when the xqf32p is programmed for parallel data output and decompression is not enabled. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 12 ?product obsolete / under obsolescence? dc electrical characteristics absolute maximum ratings supply voltage requirements for power-on reset and power-down ta bl e 7 : absolute maximum ratings symbol description xqf32p units v ccint internal supply voltage rela tive to gnd ?0.5 to +2.7 v v cco i/o supply voltage relative to gnd ?0.5 to +4.0 v v ccj jtag i/o supply voltage relative to gnd ?0.5 to +4.0 v v in input voltage with respect to gnd ?0.5 to +3.6 v v ts voltage applied to high-z output ?0.5 to +3.6 v t stg storage temperature (ambient) ?65 to +150 c t j junction temperature +125 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, t he device pins can undershoot to ?2.0v or overshoot to +7.0v, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time adversely affects device reliability. 3. for soldering guidelines, see ug112 , device packaging and thermal characteristics as well as other information at www.xilinx.com . ta bl e 8 : supply voltage requirements for power-on reset and power-down symbol description xqf32p units min max t vcc v ccint rise time from 0v to nominal voltage (2) 0.2 50 ms v ccpor por threshold for the v ccint supply 0.5 ? v t oer oe/reset release delay following por (3) 0.5 30 ms v ccpd power-down threshold for v ccint supply ? 0.5 v t rst time required to trigger a device reset when the vccint supply drops below the maximum v ccpd threshold 10 ? ms notes: 1. v ccint , v cco , and v ccj supplies can be applied in any order. 2. at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified t vcc rise time. if the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. see figure 5, page 10 . 3. if the v ccint and v cco supplies do not reach their respective recommended operating conditions before the oe/reset pin is released, then the configuration data from the prom is not be available at the recommended threshold levels. the configuration sequence m ust be delayed until both v ccint and v cco have reached their recommended operating conditions. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 13 ?product obsolete / under obsolescence? recommended operating conditions quality and reliability characteristics ta bl e 9 : recommended operating conditions symbol description xqf32p units min typ max v ccint internal voltage supply 1.65 1.8 2.0 v v cco supply voltage for output dr ivers 3.3v operation 3.0 3.3 3.6 v 2.5v operation 2.3 2.5 2.7 v 1.8v operation 1.7 1.8 1.9 v v ccj supply voltage for jtag output drivers 3.3v operation 3.0 3.3 3.6 v 2.5v operation 2.3 2.5 2.7 v v il low-level input voltage 3.3v operation 0 ? 0.8 v 2.5v operation 0 ? 0.7 v 1.8v operation ? ? 20% v cco v v ih high-level input voltage 3.3v operation 2.0 ? 3.6 v 2.5v operation 1.7 ? 3.6 v 1.8v operation 70% v cco ?3.6v t in input signal transition time (1) ??500ns v o output voltage 0 ? v cco v t a operating ambient temperature ?55 125 c notes: 1. input signal transition time measured between 10% v cco and 90% v cco . ta bl e 1 0 : quality and reliability characteristics symbol description min max units t dr data retention 20 ? years n pe program/erase cycles (endurance) 20,000 ? cycles v esd electrostatic discharge (esd) 2,000 ? v s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 14 ?product obsolete / under obsolescence? dc characteristics over operating conditions ta bl e 1 1 : dc characteristics over operating conditions symbol description xqf32p units test conditions min max v oh high-level output voltage for 3.3v outputs i oh =?4ma 2.4 ? v high-level output voltage for 2.5v outputs i oh =?500 av cco ? 0.4 ? v high-level output voltage for 1.8v outputs i oh = ?50 av cco ? 0.4 ? v v ol low-level output voltage for 3.3v outputs i ol =4ma ? 0.4 v low-level output voltage for 2.5v outputs i ol = 500 a?0.4v low-level output voltage for 1.8v outputs i ol =50 a?0.4v i ccint internal voltage supply current, active mode 33 mhz ? 10 ma i cco (1) output driver supply current, active serial mode 33 mhz ? 10 ma output driver supply current, active parallel mode 33 mhz ? 40 ma i ccj jtag supply current, active mode note (2) ?5ma i ccints internal voltage supply current, standby mode note (3) ?1ma i ccos output driver supply current, standby mode note (3) ?1ma i ccjs jtag supply current, standby mode note (3) ?1ma i ilj jtag pins tms, tdi, and tdo pull-up current v ccj = max v in = gnd ?100 a i il input leakage current v ccint = max v cco = max v in = gnd or v cco ?10 10 a i ih input and output high-z leakage current v ccint = max v cco = max v in = gnd or v cco ?10 10 a i ilp source current through internal pull-ups on en_ext_sel , rev_sel0, rev_sel1 v ccint = max v cco = max v in = gnd or v cco ?100 a i ihp sink current through internal pull-down on busy v ccint = max v cco = max v in = gnd or v cco ?100 ? a c in input capacitance v in = gnd f = 1.0 mhz ?8pf c out output capacitance v in = gnd f = 1.0 mhz ?14pf notes: 1. output driver supply current specification based on no-load conditions. 2. tdi/tms/tck non-static (active). 3. ce high, oe low, and tms/tdi/tck static. s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 15 ?product obsolete / under obsolescence? ac electrical characteristics ac characteristics over operating conditions xqf32p prom as configuration slave with clk input pin as clock source x-ref target - figure 6 figure 6: xqf32p prom as configuration slave with clk input pin as clock source ta bl e 1 2 : xqf32p prom as configuration slave with clk input pin as clock source symbol description xqf32p units min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (9) 300 ? ns cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (9) 300 ? ns t cf cf to data delay when vcco = 3.3v or 2.5v (8) ?25ns cf to data delay when vcco = 1.8v (8) ?25ns t oe oe/reset to data delay (5) when v cco = 3.3v or 2.5v ? 30 ns oe/reset to data delay (5) when v cco = 1.8v ? 30 ns t ce ce to data delay (4) when v cco = 3.3v or 2.5v ? 30 ns ce to data delay (4) when v cco = 1.8v ? 30 ns t cac clk to data delay (7) when v cco = 3.3v or 2.5v ? 30 ns clk to data delay (7) when v cco = 1.8v ? 30 ns t oh data hold from ce , oe/reset , clk, or cf when v cco = 3.3v or 2.5v (8) 5?ns data hold from ce , oe/reset , clk, or cf when v cco = 1.8v (8) 5?ns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ? 45 ns ce or oe/reset to data float delay (2) when v cco = 1.8v ? 45 ns ce oe/re s et clk bu s y (option a l) data t ce t lc t hc t s ce t oe t cac t hce t hoe t cyc t oh t df t oh t hb t s b cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv d s 541_06_012011 t s xt t hxt t s rv t hrv t cf t hcf s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 16 ?product obsolete / under obsolescence? t cyc clock period (6) (serial mode) when v cco = 3.3v or 2.5v 30 ? ns clock period (6) (serial mode) when v cco = 1.8v 30 ? ns clock period (6) (parallel mode) when v cco = 3.3v or 2.5v 35 ? ns clock period (6) (parallel mode) when v cco = 1.8v 35 ? ns t lc clk low time (3) when v cco = 3.3v or 2.5v 12 ? ns clk low time (3) when v cco = 1.8v 12 ? ns t hc clk high time (3) when v cco = 3.3v or 2.5v 12 ? ns clk high time (3) when v cco = 1.8v 12 ? ns t sce ce setup time to clk (guarantees proper counting) (3) when v cco = 3.3v or 2.5v 30 ? ns ce setup time to clk (guarantees proper counting) (3) when v cco = 1.8v 30 ? ns t hce ce hold time (guarantees counters are reset) (4) when v cco = 3.3v or 2.5v 2000 ? ns ce hold time (guarantees counters are reset) (4) when v cco = 1.8v 2000 ? ns t hoe oe/reset hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 2000 ? ns oe/reset hold time (guarantees counters are reset) (5) when v cco = 1.8v 2000 ? ns t sb busy setup time to clk when v cco = 3.3v or 2.5v (8) 12 ? ns busy setup time to clk when v cco = 1.8v (8) 12 ? ns t hb busy hold time to clk when v cco = 3.3v or 2.5v (8) 8?ns busy hold time to clk when v cco = 1.8v (8) 8?ns t sxt en_ext_sel setup time to cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) 300 ? ns en_ext_sel setup time to cf, ce or oe/reset when v cco = 1.8v (8) 300 ? ns t hxt en_ext_sel hold time from cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) 300 ? ns en_ext_sel hold time from cf, ce or oe/reset when v cco = 1.8v (8) 300 ? ns t srv rev_sel setup time to cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) 300 ? ns rev_sel setup time to cf, ce or oe/reset when v cco = 1.8v (8) 300 ? ns t hrv rev_sel hold time from cf, ce or oe/reset when v cco = 3.3v or 2.5v (8) 300 ? ns rev_sel hold time from cf, ce or oe/reset when v cco = 1.8v (8) 300 ? ns notes: 1. ac test load = 30 pf for xqf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady-state active levels. 3. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 4. if t hce high < 2 s, t ce = 2 s. 5. if t hoe low < 2 s, t oe = 2 s. 6. this is the minimum possible t cyc . actual t cyc = t cac + fpga data setup time. example: with the xcf32p in serial mode with v cco at 3.3v, if fpga data setup time = 15 ns, then the actual t cyc = 25 ns +15 ns = 40 ns. 7. guaranteed by design; not tested. 8. cf, en_ext_sel, rev_sel[ 1:0], and busy are inputs. 9. when jtag config command is issued, prom drives cf low for at least the t hcf minimum. ta bl e 1 2 : xqf32p prom as configuration slave with clk input pin as clock source (cont?d) symbol description xqf32p units min max s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 17 ?product obsolete / under obsolescence? xqf32p prom as configuration master with clk input pin as clock source x-ref target - figure 7 figure 7: xqf32p prom as configuration master with clk input pin as clock source ta bl e 1 3 : xqf32p prom as configuration master with clk input pin as clock source symbol description xqf32p units min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (11) 300 ? ns cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (11) 300 ? ns t cf cf to data delay when v cco = 3.3v or 2.5v ? 25 ns cf to data delay when v cco = 1.8v ? 25 ns t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v ? 30 ns oe/reset to data delay (6) when v cco = 1.8v ? 30 ns t ce ce to data delay (5) when v cco = 3.3v or 2.5v ? 30 ns ce to data delay (5) when v cco = 1.8v ? 30 ns t eoh data hold from ce , oe/reset , or cf when v cco = 3.3v or 2.5v 5 ? ns data hold from ce , oe/reset , or cf when v cco = 1.8v 5 ? ns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ? 45 ns ce or oe/reset to data float delay (2) when v cco = 1.8v ? 45 ns t cyco clock period (7) (serial mode) when v cco = 3.3v or 2.5v 30 ? ns clock period (7) (serial mode) when v cco = 1.8v 30 ? ns clock period (7) (parallel mode) when v cco = 3.3v or 2.5v 35 ? ns clock period (7) (parallel mode) when v cco = 1.8v 35 ? ns ce oe/re s et clk clkout bu s y (option a l) data t ce t lc t hc t oe t hce t hoe t cyco t hb t s b t oecc t cecc t clko t coh t ccdd d s 541_07_020 8 11 t eoh t df note: 8 clkout cycle s a re o u tp u t a fter ce ri s ing edge, b efore clkout i s 3 - s t a ted, if oe/re s et rem a in s high, a nd termin a l co u nt h as not b een re a ched. cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv t s xt t hxt t s rv t hrv t cf t cfcc t ddc t hcf s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 18 ?product obsolete / under obsolescence? t lc clk low time (3) when v cco = 3.3v or 2.5v 12 ? ns clk low time (3) when v cco = 1.8v 12 ? ns t hc clk high time (3) when v cco = 3.3v or 2.5v 12 ? ns clk high time (3) when v cco = 1.8v 12 ? ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 2000 ? ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 2000 ? ns t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 2000 ? ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 2000 ? ns t sb busy setup time to clkout when v cco = 3.3v or 2.5v 12 ? ns busy setup time to clkout when v cco = 1.8v 12 ? ns t hb busy hold time to clkout when v cco = 3.3v or 2.5v 8 ? ns busy hold time to clkout when v cco = 1.8v 8 ? ns t clko clk input to clkout output delay when v cco = 3.3v or 2.5v ? 35 ns clk input to clkout output delay when v cco = 1.8v ? 35 ns clk input to clkout output delay when v cco = 3.3v or 2.5v with decompression (10) ?35ns clk input to clkout output delay when v cco = 1.8v with decompression (10) ?35ns t cecc ce to clkout delay (8) when v cco = 3.3v or 2.5v 0 2 clk cycles ? ce to clkout delay (8) when v cco = 1.8v 0 2 clk cycles ? t oecc oe/reset to clkout delay (8) when v cco = 3.3v or 2.5v 02 clk cycles ? oe/reset to clkout delay (8) when v cco = 1.8v 02 clk cycles ? t cfcc cf to clkout delay (8) when v cco = 3.3v or 2.5v 0 ? ns cf to clkout delay (8) when v cco = 1.8v 0 ? ns t ccdd clkout to data delay when v cco = 3.3v or 2.5v (9) ?32ns clkout to data delay when v cco = 1.8v (9) ?32ns t ddc data setup time to clkout when v cco = 3.3v or 2.5v with decompression (9)(10) 5?ns data setup time to clkout when v cco = 1.8v with decompression (9)(10) 5?ns t coh data hold from clkout when v cco = 3.3v or 2.5v 3 ? ns data hold from clkout when v cco = 1.8v 3 ? ns data hold from clkout when v cco = 3.3v or 2.5v with decompression (10) 3?ns data hold from clkout when v cco = 1.8v with decompression (10) 3?ns t sxt en_ext_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hxt en_ext_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t srv rev_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns ta bl e 1 3 : xqf32p prom as configuration master with clk input pin as clock source (cont?d) symbol description xqf32p units min max s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 19 ?product obsolete / under obsolescence? xqf32p prom as configuration master with internal oscillator as clock source t hrv rev_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns notes: 1. ac test load = 30 pf for xqf32p. 2. float delays are measured with 5 pf ac loads.transition is measured at 200 mv from steady-state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s. 6. if t hoe low < 2 s, t oe = 2 s. 7. this is the minimum possible t cyco . actual t cyco = t ccdd + fpga data setup time. example: with the xqf32p in serial mode with v cco at 3.3v, if fpga data setup time = 15 ns, then the actual t cyco = 25 ns +15 ns = 40 ns. 8. the delay before the enabled clkout signal begins clocking data out of the device is dependent on the clocking configuration. the delay before clkout is enabled increases if decompression is enabled. 9. slower clk frequency option can be required to meet the fpga data sheet setup time. 10. when decompression is enabled, the clkout signal becomes a controlled clock output. when decompressed data is available, clk out toggles at ? the source clock frequency (either ? the selected internal clock frequency or ? the external clk input frequency). when decompressed data is not available, the clkout pin is parked high. if clkout is used, then it must be pulled high externally us ing a 4.7k pull-up to v cco . 11. when jtag config command is issued, prom drives cf low for at least the t hcf minimum. x-ref target - figure 8 figure 8: xqf32p prom as configuration master with internal oscillator as clock source ta bl e 1 3 : xqf32p prom as configuration master with clk input pin as clock source (cont?d) symbol description xqf32p units min max ce oe/re s et clkout bu s y (option a l) data t ce t oe t hce t hoe t hb t s b t oec t cec t coh t cdd d s 541_0 8 _020 8 11 t eoh t df note: 8 clkout cycle s a re o u tp u t a fter ce ri s ing edge, b efore clkout i s 3 - s t a ted, if oe/re s et rem a in s high, a nd termin a l co u nt h as not b een re a ched. cf en_ext_ s el rev_ s el[1:0] t s xt t hxt t s rv t hrv t s xt t hxt t s rv t hrv t cf t cfc t ddc t hcf s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 20 ?product obsolete / under obsolescence? ta bl e 1 4 : xqf32p prom as configuration master with internal oscillator as clock source symbol description xqf32p units min max t hcf cf hold time to guarantee design revision selection is sampled when v cco = 3.3v or 2.5v (12) 300 ? ns cf hold time to guarantee design revision selection is sampled when v cco = 1.8v (12) 300 ? ns t cf cf to data delay when v cco = 3.3v or 2.5v ? 25 ns cf to data delay when v cco = 1.8v ? 25 ns t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v ? 30 ns oe/reset to data delay (6) when v cco = 1.8v ? 30 ns t ce ce to data delay (5) when v cco = 3.3v or 2.5v ? 30 ns ce to data delay (5) when v cco = 1.8v ? 30 ns t eoh data hold from ce , oe/reset , or cf when v cco = 3.3v or 2.5v 5 ? ns data hold from ce , oe/reset , or cf when v cco = 1.8v 5 ? ns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v ? 45 ns ce or oe/reset to data float delay (2) when v cco = 1.8v ? 45 ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 2000 ? ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 2000 ? ns t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 2000 ? ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 2000 ? ns t sb busy setup time to clkout when v cco = 3.3v or 2.5v 12 ? ns busy setup time to clkout when v cco = 1.8v 12 ? ns t hb busy hold time to clkout when v cco = 3.3v or 2.5v 8 ? ns busy hold time to clkout when v cco = 1.8v 8 ? ns t cec ce to clkout delay (7) when v cco = 3.3v or 2.5v 0 1 s ce to clkout delay (7) when v cco = 1.8v 0 1 s t oec oe/reset to clkout delay (7) when v cco = 3.3v or 2.5v 0 1 s oe/reset to clkout delay (7) when v cco = 1.8v 0 1 s t cfc cf to clkout delay (7) when v cco = 3.3v or 2.5v 0 ? ns cf to clkout delay (7) when v cco = 1.8v 0 ? ns t cdd clkout to data delay when v cco = 3.3v or 2.5v (8) ?30ns clkout to data delay when v cco = 1.8v (8) ?30ns t ddc data setup time to clkout when v cco = 3.3v or 2.5v with decompression (8)(11) 5?ns data setup time to clkout when v cco = 1.8v with decompression (8)(11) 5?ns t coh data hold from clkout when v cco = 3.3v or 2.5v 3 ? ns data hold from clkout when v cco = 1.8v 3 ? ns data hold from clkout when v cco = 3.3v or 2.5v with decompression (11) 3?ns data hold from clkout when v cco = 1.8v with decompression (11) 3?ns t sxt en_ext_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hxt en_ext_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns en_ext_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 21 ?product obsolete / under obsolescence? t srv rev_sel setup time to cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel setup time to cf , ce , or oe/reset when v cco = 1.8v 300 ? ns t hrv rev_sel hold time from cf , ce , or oe/reset when v cco = 3.3v or 2.5v 300 ? ns rev_sel hold time from cf , ce , or oe/reset when v cco = 1.8v 300 ? ns ff clkout default (fast) frequency (9) 25 50 mhz clkout default (fast) frequency with decompression (11) 12.5 25 mhz fs clkout alternate (slower) frequency (10) 12.5 25 mhz clkout alternate (slower) frequency with decompression (11) 6 12.5 mhz notes: 1. ac test load = 30 pf for xqf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady-state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s. 6. if t hoe low < 2 s, t oe = 2 s. 7. the delay before the enabled clkout signal begins clocking data out of the device is dependent on the clocking configuration. the delay before clkout is enabled increases if decompression is enabled. 8. slower clk frequency option can be required to meet the fpga data sheet setup time. 9. typical clkout default (fast) period = 25 ns (40 mhz) 10. typical clkout alternate (slower) period = 50 ns (20 mhz) 11. when decompression is enabled, the clkout signal becomes a controlled clock output. when decompressed data is available, clk out toggles at ? the source clock frequency (either ? the selected internal clock frequency or ? the external clk input frequency). when decompressed data is not available, the clkout pin is parked high. if clkout is used, then it must be pulled high externally us ing a 4.7k pull-up to v cco . 12. when jtag config command is issued, prom drives cf low for at least the thcf minimum. ta bl e 1 4 : xqf32p prom as configuration master with internal oscillator as clock source (cont?d) symbol description xqf32p units min max s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 22 ?product obsolete / under obsolescence? ac characteristics over operating conditions when cascading x-ref target - figure 9 figure 9: ac characteristics over operating conditions when cascading ta bl e 1 5 : ac characteristics over operating conditions when cascading symbol description xqf32p units min max t cdf clk to output float delay (2)(3) when v cco = 2.5v or 3.3v ? 25 ns clk to output float delay (2)(3) when v cco = 1.8v ? 25 ns t ock clk to ceo delay (3)(5) when v cco = 2.5v or 3.3v ? 20 ns clk to ceo delay (3)(5) when v cco = 1.8v ? 20 ns t oce ce to ceo delay (3)(6) when v cco = 2.5v or 3.3v ? 80 ns ce to ceo delay (3)(6) when v cco = 1.8v ? 80 ns t ooe oe/reset to ceo delay (3) when v cco = 2.5v or 3.3v ? 80 ns oe/reset to ceo delay (3) when v cco = 1.8v ? 80 ns t coce clkout to ceo delay when v cco = 2.5v or 3.3v ? 25 ns clkout to ceo delay when v cco = 1.8v ? 25 ns t codf clkout to output float delay when v cco = 2.5v or 3.3v ? 30 ns clkout to output float delay when v cco = 1.8v ? 30 ns notes: 1. ac test load = 30 pf for xqf32p. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. for cascaded proms, if the fpga?s dual-purpose configuration da ta pins are set to persist as configuration pins, the minimum period is increased based on the clk to ceo and ce to data propagation delays: - t cyc minimum = t ock + t ce + fpga data setup time. - t cac maximum = t ock + t ce 6. for cascaded proms, if the fpga?s dual-purpose configuration da ta pins become general i/o pins after configuration; to allow for the disable to propagate to the cascaded proms and to avoid c ontention on the data lines followi ng configuration, the minimum period is increased based on the ce to ceo and ce to data propagation delays: - t cyc minimum = t oce + t ce - t cac maximum = t ock + t ce oe/re s et ce clk clkout (option a l) data ceo t oce t ooe fir s t bit l as t bit t cdf t codf t ock t coce d s 541_17_111706 s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 23 ?product obsolete / under obsolescence? pinouts and pin descriptions xqf32p vog48 pin names and descriptions the xqf32p platform flash prom is available in the vog48 package. ta b l e 1 6 provides a list of the pin names and descriptions for the xqf32p 48-pin vog48 plastic, thin, small outline package (tsop). ta bl e 1 6 : xqf32p pin names and descriptions (vog48) pin name boundary scan order boundary scan function pin description 48-pin tsop vog48 d0 28 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. d0-d7 are the data output pins to pr ovide parallel data for configuring a xilinx fpga in selectmap (parallel) mode. the d0 output is set to a high-impe dance state during ispen (when not clamped). the d1-d7 outputs are set to a high-impedance state during ispen (when not clamped) and when serial mode is selected for configuration. the d1-d7 pins can be left unconnected when the prom is used in serial mode. 28 27 output enable d1 26 data out 29 25 output enable d2 24 data out 32 23 output enable d3 22 data out 33 21 output enable d4 20 data out 43 19 output enable d5 18 data out 44 17 output enable d6 16 data out 47 15 output enable d7 14 data out 48 13 output enable clk 01 data in configuration clock input. an internal programmable control bit selects between the internal oscillator and the clk input pin as the clock source to control the configuration sequence. each rising edge on the clk input increments the internal address counte r if the clk input is selected, ce is low, oe/reset is high, busy is low (parallel mode only), and cf is high. 12 oe/reset 04 data in output enable/reset (open-drain i/o). when low, this input holds the address counter reset and the data and clkout outputs are placed in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom completes the internal power-on reset sequence. polarity is not programmable. 11 03 data out 02 output enable ce 00 data in chip enable input. when ce is high, the device is put into low-power standby mode, the address counter is reset, and the data and clkout outputs are placed in a high-impedance state. 13 cf 11 data in configuration pulse (open-drain i/o). as an output, this pin allows the jtag config instruction to init iate fpga configuration without powering down the fpga. this is an open-drain signal that is pulsed low by the jtag config command. as an input, on the rising edge of cf , the current design revision selection is sampled and the internal address counter is reset to the start address for the selected revision. if unused, the cf pin must be pulled high using an external 4.7 k pull-up to v cco . 6 10 data out 09 output enable s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 24 ?product obsolete / under obsolescence? ceo 06 data out chip enable output. chip enable output (ceo ) is connected to the ce input of the next prom in the c hain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 10 05 output enable en_ext_sel 31 data in enable external selection input. when this pin is low, design revision selection is controlled by the revision select pins. when this pin is high, design revision selection is controlled by the internal programmable revision select cont rol bits. en_ext_sel has an internal 50k resistive pull-up to v cco to provide a logic 1 to the device if the pin is not driven. 25 rev_sel0 30 data in revision select[1:0] inputs. when the en_ext_sel is low, the revision select pins are used to select the design revision to be enabled, overriding the internal programmable revision select control bits. the revision select[1:0] inputs have an internal 50 k resistive pull-up to v cco to provide a logic 1 to the device if the pins are not driven. 26 rev_sel1 29 data in 27 busy 12 data in busy input. the busy input is enabled when parallel mode is selected for configuration. when busy is high, the internal address counter stops incrementing and the current data remains on the data pins. on the first rising edge of clk after busy transitions from high to low, the data for the next address is driven on the data pins. when serial mode or decompression is enabled during devi ce programming, the busy input is disabled. busy has an internal 50 k resistive pull-down to gnd to provide a logic 0 to the device if the pin is not driven. 5 clkout 08 data out configuration clock output. an internal programmable control bit enables the clkout signal, which is sourced from either the internal oscillator or the clk input pin. each rising edge of the selected clock source increments the internal addre ss counter if data is available, ce is low, and oe/reset is high. output data is available on the rising edge of clkout. clkout is disabled if ce is high or oe/reset is low. if decompression is enabled, clkout is parked high when decompressed data is not ready. when clkout is disabled, the clkout pin is put into a high-z state. if clkout is used, then it must be pulled high externally using a 4.7 k pull-up to v cco . 9 07 output enable tms mode select jtag mode select input. the state of tms on the rising edge of tck determines the state transit ions at the test access port (tap) controller. tms has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 21 tck clock jtag clock input. this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 20 tdi data in jtag serial data input. this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50 k resistive pull-up to v ccj to provide a logic 1 to the device if the pin is not driven. 19 tdo data out jtag serial data output. this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k resistive pull-up to v ccj to provide a logic 1 to the system if the pin is not driven. 22 vccint +1.8v supply. positive 1.8v supply voltage for internal logic. 4, 15, 34 vcco +3.3v, 2.5v, or 1.8v i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the output vo ltage drivers and input buffers. 8, 30, 38, 45 vccj +3.3v or 2.5v jtag i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the tdo output voltage driver and tck, tms, and tdi input buffers. 24 ta bl e 1 6 : xqf32p pin names and descriptions (vog48) (cont?d) pin name boundary scan order boundary scan function pin description 48-pin tsop vog48 s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 25 ?product obsolete / under obsolescence? xqf32p vog48 pinout diagram gnd ground 2, 7, 17, 23, 31, 36, 46 dnc do not connect. (these pins must be left unconnected.) 1, 3, 14, 16, 18, 35, 37, 39, 40, 41, 42 x-ref target - figure 10 figure 10: vog48 pinout diagram (top view) with pin names ta bl e 1 6 : xqf32p pin names and descriptions (vog48) (cont?d) pin name boundary scan order boundary scan function pin description 48-pin tsop vog48 d s 541_10_012611 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 2 8 27 26 25 vog4 8 to p view dnc gnd dnc vccint bu s y cf gnd vcco clkout ceo oe/re s et clk ce dnc vccint dnc gnd dnc tdi tck tm s tdo gnd d7 d6 gnd vcco d5 d4 dnc dnc dnc dnc vcco dnc gnd dnc vccint d 3 d2 gnd vcco d1 d0 rev_ s el1 rev_ s el0 en_ext_ s el vccj s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 26 ?product obsolete / under obsolescence? ordering information valid ordering combinations marking information revision history the following table shows the revision history for this document. x-ref target - figure 11c figure 11: ordering information xqf32pvog48m x-ref target - figure 12 figure 12: marking information date version revision 11/27/2006 1.0 xilinx initial release. 02/11/2011 2.0 removed table 2 from document as platform flash proms are compatible with all of the existing fpga device families. removed 1.5v v cco option from features list/table and from all specification tables. replaced verbiage in section external programming, page 3 . deleted former figure 5 through figure 12 (configuration mode schematics) and all associated text in former section prom to fpga configuration mode and connection summary . clarified ta b l e 8 . added row for t a in specification table recommended operating conditions, page 13 . removed the t oecf and t cecf specifications from ta bl e 1 3 and ta b l e 1 4 as well as and figure 7 and figure 8 . removed vo48 package per xcn09030 : product discontinuation notice: vo48 pin package in platform flash prom devices . added vog48 (pb-free) package option as required throughout data sheet. 06/25/2014 2.1 updated valid ordering combinations . updated notice of disclaimer . 08/05/2015 3.0 this product is obsolete/discontinued per xcn15008 . d s 541_11_012611 xqf 3 2p vog4 8 m operatin g ran g e/proce ss in g m = (t j = ?55c to +125c) packa g e type vog4 8 = 4 8 -pin t s op p a ck a ge, p b -free device number xqf 3 2p d s 541_12_012611 xqf 3 2p vog4 8 packa g e type vog4 8 = 4 8 -pin t s op p a ck a ge, p b -free device number xqf 3 2p s e n d f e e d b a c k defense grade platform flash in-system programmable configuration prom ds541 (v3.0) august 5, 2015 www.xilinx.com product specification 27 ?product obsolete / under obsolescence? notice of disclaimer the information disclosed to you hereunder (the ?materials?) is pr ovided solely for the selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are m ade available "as is" and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or stat utory, including but not limited to warranties of merchantability, non-infringement, or fitness for any pa rticular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under an y other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includi ng your use of the materials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of da ta, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the p ossibility of the same. xilinx assumes no obligation to correct any errors c ontained in the materials or to notify you of updates to the m aterials or to product specifications. you may not reproduc e, modify, distribute, or publicly display the materials without prior written cons ent. certain products are subject to the terms and conditions of xilinx?s limi ted warranty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of xilinx products in such critical applications, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . s e n d f e e d b a c k |
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